View PE42520MLBA-Z_7503589.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2012-2013 peregrine semiconductor corp. all rights reserved. page 1 of 16 document no. doc-12714-3 | www.psemi.com figure 2. package type 16-lead 3x3 mm qfn the pe42520 spdt absorptive rf switch is designed for use in test/ate and other high performance wireless applications. this broadband general purpose switch maintains excellent rf performance and linearity from 9 khz through 13 ghz. this switch is a pin-compatible upgraded version of pe42552 with higher power handling of 36 dbm continuous wave (cw) and 38 dbm instantaneous power in 50 ? @ 8 ghz. the pe42520 exhibits high isolation, fast settling time, and is offered in a 3x3 mm qfn package. the pe42520 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. ultracmos ? spdt rf switch 9 khz - 13 ghz product description pe42520 features ?? harp? technology enhanced ?? fast settling time ?? no gate and phase lag ?? no drift in insertion loss and phase ?? high power handling @ 8 ghz in 50 ? ?? 36 dbm cw ?? 38 dbm instantaneous power ?? 26 dbm terminated port ?? high linearity ?? 66 dbm iip3 ?? low insertion loss ?? 0.8 db @ 3 ghz ?? 0.9 db @ 10 ghz ?? 2.0 db @ 13 ghz ?? high isolation ?? 45 db @ 3 ghz ?? 31 db @ 10 ghz ?? 18 db @ 13 ghz ?? esd performance ?? 4kv hbm on rf pins to gnd ?? 2.5kv hbm on all pins ?? 1kv cdm on all pins figure 1. functional diagram product specification doc-50572
document no. doc-12714-3 | ultracmos ? rfic solutions page 2 of 16 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe42520 product specification table 1. electrical specifications @ 25c, v dd = 3.3v , vss ext = 0v or v dd = 3.4v, vss ext = -3.4v, (z s = z l = 50 ? ) unless otherwise noted parameter path condition min typ max unit operation frequency 9 khz 13 ghz as shown insertion loss rfc?rfx 9 khz ?10 mhz 10 mhz ? 3 ghz 3 ghz ? 7.5 ghz 7.5 ghz ? 10 ghz 10 ghz ? 12 ghz 12 ghz ?13 ghz 0.60 0.80 0.85 0.90 1.20 2.00 0.80 1.00 1.05 1.10 1.65 2.70 db db db db db db isolation rfx?rfx 9 khz ?10 mhz 10 mhz ? 3 ghz 3 ghz ? 7.5 ghz 7.5 ghz ? 10 ghz 10 ghz ? 12 ghz 12 ghz ?13 ghz 70 46 35 24 16 13 90 54 38 27 19 17 db db db db db db isolation rfc?rfx 9 khz ?10 mhz 10 mhz ? 3 ghz 3 ghz ? 7.5 ghz 7.5 ghz ? 10 ghz 10 ghz ? 12 ghz 12 ghz ?13 ghz 80 42 41 26 16 13 90 45 44 31 20 18 db db db db db db return loss (active port) rfc-rfx 9 khz ?10 mhz 10 mhz ? 3 ghz 3 ghz ? 7.5 ghz 7.5 ghz ? 10 ghz 10 ghz ? 12 ghz 12 ghz ?13 ghz 23 17 15 18 20 10 db db db db db db return loss (common port) rfc-rfx 9 khz ?10 mhz 10 mhz ? 3 ghz 3 ghz ? 7.5 ghz 7.5 ghz ? 10 ghz 10 ghz ? 12 ghz 12 ghz ?13 ghz 23 17 15 18 18 10 db db db db db db return loss (terminated port) rfx 9 khz ?10 mhz 10 mhz ? 3 ghz 3 ghz ? 7.5 ghz 7.5 ghz ? 10 ghz 10 ghz ? 12 ghz 12 ghz ?13 ghz 32 24 21 13 8 5 db db db db db db input 0.1 db compression point 1 rfc?rfx 10 mhz ? 13 ghz fig. 5 dbm input ip2 rfc?rfx 834 mhz, 1950 mhz 120 dbm input ip3 rfc?rfx 834 mhz, 1950 mhz, and 2700 mhz 66 dbm settling time 50% ctrl to 0.05 db final value 15 20 s switching time 50% ctrl to 90% or 10% of final value 5.5 9.5 s note 1: the input 0.1 db compression point is a linearity figure of merit. refer to table 3 for the rf input power p in (50 ? )
?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-12714-3 | www.psemi.com pe42520 page 3 of 16 product specification table 2. pin descriptions figure 3. pin configuration (top view) pin # pin name description 2 rf1 1 rf port 1 1, 3, 4, 5, 6, 8, 9, 10, 12 gnd ground 7 rfc 1 rf common 11 rf2 1 rf port 2 13 vss ext 2 external vss negative voltage control 14 ctrl digital control logic input 15 ls logic select - used to determine the definition for the ctrl pin (see table 5 ) 16 v dd supply voltage pad gnd exposed pad: ground for proper operation table 3. operating ranges parameter symbol min typ max unit supply voltage (normal mode, vss ext = 0v) 1 v dd 2.3 5.5 v supply voltage (bypass mode, vss ext = -3.4v, v dd 3.4v for full spec. compliance) 2 v dd 2.7 3.4 5.5 v supply current (bypass mode, vss ext = -3.4v) 2 i dd 50 80 a negative supply current (bypass mode, vss ext = -3.4v) 2 i ss -40 -16 a digital input high (ctrl) v ih 1.17 3.6 v digital input low (ctrl) v il -0.3 0.6 v rf input power, cw (rfc-rfx) 3 9 khz 10 mhz 10 mhz 8 ghz 8 ghz 13 ghz p in-cw fig. 4 36 fig. 5 dbm dbm dbm operating temperature range t op -40 +25 +85 c negative supply voltage (bypass mode) 2 vss ext -3.6 -3.2 v supply current (normal mode, vss ext = 0v) 1 i dd 120 200 a rf input power into terminated ports, cw (rfx) 3 9 khz 600 khz 600 khz 13 ghz p in,term fig. 4 26 dbm dbm digital input current i ctrl 10 a rf input power, pulsed (rfc-rfx) 4 9 khz 10 mhz 10 mhz 13 ghz p in-pulsed fig. 4 fig. 5 dbm dbm rf input power, hot switch, cw 3 9 khz 300 khz 300 khz 13 ghz p in-hot fig. 4 20 dbm dbm notes: 1. rf pins 2, 7, and 11 must be at 0v dc. the rf pins do not require dc blocking capacitors for proper oper ation if the 0v dc requirement is met 2. use vss ext (pin 13) to bypass and disable internal negative voltage generator. connect vss ext (pin 13) to gnd (vss ext = 0v) to enable internal negative voltage generator notes: 1. normal mode: connect vss ext (pin 13) to gnd (vss ext = 0v) to enable internal negative voltage generator 2. bypass mode: use vss ext (pin 13) to bypass and disable internal negative voltage generator 3. 100% duty cycle, all bands, 50 ? 4. pulsed, 5% duty cycle of 4620 s period, 50 ?
document no. doc-12714-3 | ultracmos ? rfic solutions page 4 of 16 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe42520 product specification electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. table 5. control logic truth table logic select (ls) the logic select feature is used to determine the definition for the ctrl pin. switching frequency the pe42520 has a maximum 25 khz switching rate when the internal negative voltage generator is used (pin 13 = gnd). the rate at which the pe42520 can be switched is only limited to the switching time ( table 1 ) if an external negative supply is provided (pin 13 = vss ext ). switching frequency describes the time duration between switching events. switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. ls ctrl rfc-rf1 rfc-rf2 0 0 off on 0 1 on off 1 0 on off 1 1 off on moisture sensitivity level the moisture sensitivity level rating for the pe42520 in the 16-lead 3x3 mm qfn package is msl3. optional external vss control (vss ext ) for proper operation, the vss ext control pin must be grounded or tied to the vss voltage specified in table 3 . when the vss ext control pin is grounded, fets in the switch are biased with an internal negative voltage generator. for applications that require the lowest possible spur performance, vss ext can be applied externally to bypass the internal negative voltage generator. spurious performance the typical spurious performance of the pe42520 is -152 dbm when vss ext = 0v (pin 13 = gnd). if further improvement is desired, the internal negative voltage generator can be disabled by setting vss ext = -3.4v. table 4. absolute maximum ratings parameter/condition symbol min max unit supply voltage v dd -0.3 5.5 v digital input voltage (ctrl) v ctrl -0.3 3.6 v rf input power, cw (rfc-rfx) 1 9 khz 10 mhz 10 mhz 8 ghz 8 ghz 13 ghz p in-cw fig. 4 36 fig. 5 dbm dbm dbm storage temperature range t st -65 150 c esd voltage hbm 3 rf pins to gnd all pins v esd,hbm 4000 2500 v v esd voltage mm 4 , all pins v esd,mm 200 v ls input voltage v ls -0.3 3.6 v esd voltage cdm 5 , all pins v esd,cdm 1000 v rf input power into terminated ports, cw (rfx) 1 9 khz 10 mhz 10 mhz 13 ghz p in,term fig. 4 26 dbm dbm rf input power, pulsed (rfc-rfx) 2 9 khz 10 mhz 10 mhz 13 ghz p in-pulsed fig. 4 fig. 5 dbm dbm notes: 1. 100% duty cycle, all bands, 50 ? 2. pulsed, 5% duty cycle of 4620 s period, 50 ? 3. human body model (mil-std 883 method 3015) 4. machine model (jedec jesd22-a115) 5. charged device model (jedec jesd22-c101) exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability.
?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-12714-3 | www.psemi.com pe42520 page 5 of 16 product specification figure 4. power de-rating curve for 9 khz ? 10 mhz (50 ? ) \ 5 0 5 10 15 20 25 30 35 40 1 10 100 1000 10000 input ? power ? (dbm) frequency ? (khz) max. ? rf ? input ? power, ? cw ? and ? pulsed, ? ( \ 40c ? to ? +85c ? ambient)
document no. doc-12714-3 | ultracmos ? rfic solutions page 6 of 16 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe42520 product specification 33 33.5 34 34.5 35 35.5 36 36.5 37 37.5 38 38.5 39 39.5 40 012345678910111213 input ? power ? (dbm) frequency ? (ghz) ?? p0.1db ? compression ? @ ? 25c ? ambient ?? max. ? rf ? input ? power, ? pulsed ? @ ? 25c ? ambient ?? max. ? rf ? input ? power, ? cw ? @ ? 25c ? ambient 0.01 33 33.5 34 34.5 35 35.5 36 36.5 37 37.5 38 38.5 39 39.5 40 012345678910111213 input ? power ? (dbm) frequency ? (ghz) ?? p0.1db ? compression ? @ ? 85c ? ambient ?? max. ? rf ? input ? power, ? pulsed ? @ ? 85c ? ambient ?? max. ? rf ? input ? power, ? cw ? @ ? 85c ? ambient 0.01 figure 5a. power de-rating curve for 10 mhz ? 13 ghz @ 25c ambient (50 ? ) figure 5b. power de-rating curve for 10 mhz ? 13 ghz @ 85c ambient (50 ? )
?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-12714-3 | www.psemi.com pe42520 page 7 of 16 product specification typical performance data @ 25c and v dd = 3.4v unless otherwise specified ? figure 6. insertion loss vs. temp (rfc?rf1) ? figure 7. insertion loss vs. v dd (rfc?rf1) ? figure 8. insertion loss vs. temp (rfc?rf2) ? figure 9. insertion loss vs. v dd (rfc?rf2) ?
document no. doc-12714-3 | ultracmos ? rfic solutions page 8 of 16 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe42520 product specification figure 10. rfc port return loss vs. temp (rf1 active) ? figure 11. rfc port return loss vs. v dd (rf1 active) ? figure 12. rfc port return loss vs. temp (rf2 active) ? figure 13. rfc port return loss vs. v dd (rf2 active) ? typical performance data @ 25c and v dd = 3.4v unless otherwise specified ?
?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-12714-3 | www.psemi.com pe42520 page 9 of 16 product specification figure 14. active port return loss vs. temp (rf1 active) ? figure 15. active port return loss vs. v dd (rf1 active) ? figure 16. active port return loss vs. temp (rf2 active) ? figure 17. active port return loss vs. v dd (rf2 active) ? typical performance data @ 25c and v dd = 3.4v unless otherwise specified ?
document no. doc-12714-3 | ultracmos ? rfic solutions page 10 of 16 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe42520 product specification figure 18. terminated port return loss vs. temp (rf1 active) ? figure 19. terminated port return loss vs. v dd (rf1 active) ? figure 20. terminated port return loss vs. temp (rf2 active) ? figure 21. terminated port return loss vs. v dd (rf2 active) ? typical performance data @ 25c and v dd = 3.4v unless otherwise specified ?
?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-12714-3 | www.psemi.com pe42520 page 11 of 16 product specification typical performance data @ 25c and v dd = 3.4v unless otherwise specified ? figure 23. isolation vs. v dd (rf1?rf2, rf1 active) ? figure 22. isolation vs. temp (rf1?rf2, rf1 active) ? figure 25. isolation vs. v dd (rf2?rf1, rf2 active) ? figure 24. isolation vs. temp (rf2?rf1, rf2 active) ?
document no. doc-12714-3 | ultracmos ? rfic solutions page 12 of 16 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe42520 product specification figure 26. isolation vs. temp (rfc?rf2, rf1 active) ? figure 27. isolation vs. v dd (rfc?rf2, rf1 active) ? figure 28. isolation vs. temp (rfc?rf1, rf2 active) ? figure 29. isolation vs. v dd (rfc?rf1, rf2 active) ? typical performance data @ 25c and v dd = 3.4v unless otherwise specified ?
?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-12714-3 | www.psemi.com pe42520 page 13 of 16 product specification evaluation kit the spdt switch evaluation board was designed to ease customer evaluation of peregrine?s pe42520. the rf common port is connected through a 50 ? transmission line via the sma connector, j1. rf1 and rf2 ports are connected through 50 ? transmission lines via sma connectors j2 and j3, respectively. a 50 ? through transmission line is available via sma connectors j5 and j6, which can be used to de-embed the loss of the pcb. j4 provides dc and digital inputs to the device. for the true performance of the pe42520 to be realized, the pcb should be designed in such a way that rf transmission lines and sensitive dc i/o traces are heavily isolated from one another. figure 30. evaluation kit layout ? prt-30186
document no. doc-12714-3 | ultracmos ? rfic solutions page 14 of 16 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe42520 product specification figure 31. evaluation board schematic ? notes: 1. use prt-30186-02 pcb 2. caution: contains parts and assemblies susceptible to damage by electrostatic discharge (esd) doc-12726
?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-12714-3 | www.psemi.com pe42520 page 15 of 16 product specification top view side view bottom view 3.00 3.00 pin#1corner 1.700.05 0.80 max 0.05 0.203 recommended land pattern 13 16 1 4 5 9 8 12 1.700.05 0.50 0.230.05 (x16) 1.50 0.3750.05 (x16) 1.75 3.40 3.40 0.10 c a b 0.05 c a 0.10 c (2x) c 0.10 c 0.05 c seating plane b all features 0.10 c (2x) 0.575 (x16) 0.28 (x16) 0.50 1.75 (x12) figure 32. package drawing 16-lead 3x3 mm qfn doc-01881 figure 33. top marking specifications 42520 yyww zzzzz 17-0009 = pin 1 designator yyww = date code zzzzz = last five digits of lot number
document no. doc-12714-3 | ultracmos ? rfic solutions page 16 of 16 ?2012-2013 peregrine semiconductor corp. all rights reserved. pe42520 product specification tape feed direction device orientation in tape top of device pin 1 advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com . figure 34. tape and reel specifications notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. camber in compliance with eia 481 3. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole ao = 3.30 bo = 3.30 ko = 1.10 table 6. ordering information order code description package shipping method PE42520MLBA-Z pe42520 spdt rf switch green 16-lead 3x3 mm qfn 3000 units / t&r ek42520-02 pe42520 evaluation ki t evaluation kit 1 / box

▲Up To Search▲

Price & Availability of PE42520MLBA-Z

	To Download PE42520MLBA-Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .